\section{Motivation}\label{motivation}
In this section, we first describe the RF harvesting sensor nodes with nvSRAM. Then we analyze the limitation of conventional backup processes.
\begin{figure}[!hpt]
\centering
\includegraphics[scale = 0.42]{RFharvesting.pdf}
\caption{RF harvesting nonvolatile sensor node architecture}\label{fig1}
\end{figure}

Fig.~\ref{fig1} shows a typical RF harvesting nonvolatile sensor node architecture used in bridge health monitoring. The matching circuit along with a AC-DC rectifier and a voltage multiplier generates proper DC voltage for the charging and backup controller~\cite{Jabbar2010Consumer}. The charging controller distributes the DC power to recharge the energy storage capacitor (denoted as $C_{ES}$) or run the nonvolatile sensor node. The nonvolatile sensor consists of a nonvolatile MCU chip and several sensors such as temperature sensors and acceleration sensor. The transceiver is used to communicate with other nodes. Flash is used as the off-chip instruction and data memory. The NV MCU chip is composed of a nonvolatile processor (NVP) and a nonvolatile SRAM. $C_{ES}$ supplies power to the NVP and nvSRAM in order to guarantee data backup process after power down. The backup controller detects power failure and generates the backup signal to enable the backup process.

\input{tab_capacitor}

On-chip memory of enough capacity is needed on the sensor node to assist real-time monitoring and computing. However, large capacity of nvSRAM leads to numerous drawbacks. Tab.~\ref{capacitor} shows the backup energy, inrush current and the capacitor characteristics for different nvSRAM capacity when VDD=3.3V. NVP is modeled as THU1010N fabricated using ROHM's 0.13$\mu$ CMOS-ferroelectric hybrid process. nvSRAM is modeled using the parameters from~\cite{chiu2012low}. Note that with increasing of nvSRAM capacity from 1KB to 64KB, backup energy and inrush current increases by 15.7X and 65.6X respectively. Considering a on-chip cache configured as the 32KB data cache in ARM-cortex A8 processors~\cite{ARM}, backup energy is as large as 249nJ, which requires a 107.1nF on-chip capacitor to supply the backup energy. This capacitor results in 4.8X area overhead compared compared with the chip without the backup capacitor. Moreover, it needs 549ms to be charged to full. Long charging time reduces the QoS and harm the robustness to intermittent power input. For example, if the average power-on time is less than 500ms, the system will never work. Another concern of large capacity is high inrush current, which reaches to the ampere-level when capacity is more than 8KB. It directly limits the maximum nvSRAM block size.



